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CAT9552
16-Channel I2C-bus LED Driver with Programmable Blink Rate
FEATURES
16 LED drivers with On/Off and programmable blink rate control 2 selectable, programmable blink rates: - frequency: 0.172Hz to 44Hz - duty cycle: 0% to 99.6% 16 open drain outputs drive 25mA each I/Os can be used as GPIOs 400kHz I2C bus compatible 2.3V to 5.5V operation 5V tolerant I/Os Active low reset input RoHS-compliant 24-Lead SOIC, TSSOP and 24-pad TQFN (4 x 4mm) packages
DESCRIPTION
The CAT9552 is a 16-channel, parallel input/output port expander optimized for LED On/Off and blinking control. Each individual LED may be turned ON, OFF, or set to blinking at one of two programmable rates. The CAT9552 is compatible with I2C and SMBus applications where it is desireable to limit the bus traffic or free-up the bus master's internal timer. Three address pins allow up to eight CAT9552 devices to occupy the same bus. The CAT9552 contains an internal oscillator and two PWM signals, which drive the LED outputs. The user may program the period and duty cycle for each individual PWM signal. After an initial set-up command to program the Blink Rate 1 and Blink Rate 2 (frequency and duty cycle), only one command from the bus master is required to turn each individual open drain output ON, OFF, or cycle at Blink Rate 1 or Blink Rate 2. Each open drain LED output can sink a maximum current of 25mA. The total continuous current sunk by all I/Os must not exceed 200mA per package.
APPLICATIONS
Office machines Appliance control panels Alarm systems Point of sale displays
TYPICAL APPLICATION CIRCUIT
5V 5V
For Ordering Information details, see page 16.
3 x 10k VCC LED0 LED1 RS0 RS1 RS11
SDA SCL RESET I2C/SMBus Master
SDA SCL
RESET
CAT9552 LED11 A2 A1 A0 VSS LED15 LED12 GPIOs
Notes: LED0 to LED11 are shown being used as LED drivers LED12 to LED15 are used as standard GPIOs
(c) 2008 SCILLC. All rights reserved Characteristics subject to change without notice
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Doc. No. MD-9005 Rev B
CAT9552 PIN CONFIGURATION
SOIC (W), TSSOP (Y)
24 A2 23 A1
TQFN (HV6)
20 SDA 19 SCL 21 VCC 22 A0
AO A1 A2 LED0 LED1 LED2 LED3 LED4 LED5 LED6 LED7 VSS
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 19 17 16 15 14 13
VCC SDA SCL RESET LED15 LED14 LED13 LED12 LED11 LED10 LED9 LED8
LED2 3 LED3 4 LED4 5 LED5 6 LED0 1 LED1 2
18 RESET 17 LED15 16 LED14 15 LED13 14 LED12 13 LED11
LED8 10 LED10 12 LED9 11 LED6 7 LED7 8 VSS 9
PIN DESCRIPTION
SOIC / TSSOP 1 2 3 4-11 12 13-20 21 22 23 24 -- TQFN 22 23 24 1-8 9 10-17 18 19 20 21 Pad PIN NAME AO A1 A2 LED0 - LED7 VSS LED8 - LED15 RESET SCL SDA VCC Backside pad FUNCTION Address Input 0 Address Input 1 Address Input 2 LED Driver Output 0 to 7, I/O Port 0 to 7 Ground LED Driver Output 8 to 15, I/O Port 8 to 15 Reset Input Serial Clock Serial Data Power Supply For enhanced heat dissipation. Electrically this pad must be at ground potential.
BLOCK DIAGRAM
A2 A1 A0
VCC RESET SCL SDA
POWER ON RESET I2C BUS CONTROL
INPUT REGISTER LED SELECT (LSx) REGISTER
INPUT FILTERS
LEDx PRESCALER 0 REGISTER OSCILLATOR VSS PRESCALER 1 REGISTER PWM 1 REGISTER BLINK 1 PWM 0 REGISTER BLINK 0 CONTROL LOGIC
Note: Only one I/O is shown for clarity
CAT9552
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(c) 2008 SCILLC. All rights reserved Characteristics subject to change without notice
CAT9552 ABSOLUTE MAXIMUM RATINGS (1)
Parameters VCC with Respect to Ground Voltage on Any Pin with Respect to Ground DC Current on I/Os Supply Current Package Power Dissipation Capability (TA = 25C) Junction Temperature Storage Temperature Lead Soldering Temperature (10 seconds) Operating Ambient Temperature Ratings -2.0 to +7.0 -0.5 to +5.5 25 200 1.0 +150 -65 to +150 300 -40 to +85 Units V V mA mA W C C C C
Notes: (1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(c) 2008 SCILLC. All rights reserved Characteristics subject to change without notice
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Doc. No. MD-9005 Rev B
CAT9552 D.C. OPERATING CHARACTERISTICS
VCC = 2.3 to 5.5V, VSS = 0V; TA = -40C to +85C, unless otherwise specified Symbol Supplies VCC ICC Istb Istb VPOR
(1)
Parameter Supply Voltage Supply Current Standby Current Additional Standby Current Power-on Reset Voltage
Conditions
Min 2.3
Typ -- 250 2.1 -- 1.5
Max 5.5 550 5.0 2 2.2
Unit V A A mA V
Operating mode; VCC = 5.5V; no load; fSCL = 100kHz Standby mode; VCC = 5.5V; no load; VI = VSS or VCC, fSCL = 0kHz Standby mode; VCC = 5.5V; every LED I/O = VIN = 4.3V, fSCL = 0kHz VCC = 3.3V, No load; VI = VCC or VSS
-- -- -- --
SCL, SDA, RESET VIL
(2) (2)
Low Level Input Voltage High Level Input Voltage Low Level Output Current Leakage Current Input Capacitance Output Capacitance Low Level Input Voltage High Level Input Voltage Input Leakage Current Low Level Input Voltage High Level Input Voltage VOL = 0.4V; VCC = 2.3V VOL = 0.4V; VCC = 3.0V VOL = 0.4V; VCC = 5.0V VOL = 0.7V; VCC = 2.3V VOL = 0.7V; VCC = 3.0V VOL = 0.7V; VCC = 5.0V VOL = 0.4V VI = VCC = VSS VI = VSS VO = VSS
-0.5 0.7 VCC 3 -1 -- -- -0.5 2.0 -1 -0.5 2.0 9 12 15 15 20 25 -1 --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
0.3 VCC 5.5 -- +1 6 8 0.8 5.5 1 0.8 5.5 -- -- -- -- -- -- 1 8
V V mA A pF pF V V A V V
VIH
IOL IIL CI
(3) (3)
CO VIL
A0, A1, A2
(2) (2)
VIH I/Os VIL
IIL
(2) (2)
VIH
IOL
(4)
Low Level Output Current
mA
IIL
(3) CI/O
Input Leakage Current Input/Output Capacitance
VCC = 3.6V; VI = VSS or VCC
A pF
Notes: (1) VDD must be lowered to 0.2V in order to reset the device. (2) VIL min and VIH max are reference values only and are not tested. (3) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. (4) The output current must be limited to a maximum 25mA per each I/O; the total current sunk by all I/O must be limited to 200mA (or 100mA for eight I/Os)
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(c) 2008 SCILLC. All rights reserved Characteristics subject to change without notice
CAT9552
A.C. CHARACTERISTICS
VCC = 2.3V to 5.5V, TA = -40C to +85C, unless otherwise specified (1) Symbol FSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF
(2) (2)
Parameter Clock Frequency START Condition Hold Time Low Period of SCL Clock High Period of SCL Clock START Condition Setup Time Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time STOP Condition Setup Time Bus Free Time Between STOP and START SCL Low to Data Out Valid Data Out Hold Time Noise Pulse Filtered at SCL and SDA Inputs Parameter Output Data Valid Input Data Setup Time Input Data Hold Time Reset Pulse Width Reset Recovery Time Time to Reset
Standard I2C Min 4 4.7 4 4.7 0 250 1000 300 4 4.7 3.5 100 100 Max 100
Fast I2C Min 0.6 1.3 0.6 0.6 0 100 300 300 0.6 1.3 0.9 50 100 Min Max 200 100 1 10 0 400 Max 400
Units kHz s s s s s ns ns ns s s s ns ns Units ns ns s ns ns ns
tSU:STO tBUF
(2)
tAA tDH Ti
(2)
Symbol tPV tPS tPH Reset tW(2) tREC tRESET
(3)
Port Timing
Notes: (1) Test conditions according to "AC Test Conditions" table. (2) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. (3) The full delay to reset the part will be the sum of tRESET and the RC time constant of the SDA line.
(c) 2008 SCILLC. All rights reserved Characteristics subject to change without notice
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Doc. No. MD-9005 Rev B
CAT9552 AC TEST CONDITIONS
Input Pulse Voltage Input Rise and Fall Times Input Reference Voltage Output Reference Voltage Output Load 0.2VCC to 0.8VCC 5ns 0.3VCC, 0.7VCC 0.5VCC Current source: IOL = 3mA; 400pF for fSCL(max) = 400kHz
tF tLOW SCL tSU:STA tHD:STA
tHIGH tLOW
tR
tHD:DAT
tSU:DAT
tSU:STO
SDA IN tAA SDA OUT tDH tBUF
Figure 1. 2-Wire Serial Interface Timing
PIN DESCRIPTION
SCL: Serial Clock The serial clock input clocks all data transferred into or out of the device. The SCL line requires a pull-up resistor if it is driven by an open drain output. SDA: Serial Data/Address The bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. A pullup resistor must be connected from SDA line to VCC. LED0 to LED15: LED Driver Outputs / General Purpose I/Os These pins are open drain outputs used to directly drive LEDs. Any of these pins can be programmed to drive the LED ON, OFF, or to Blink Rate1 or Blink Rate2. A current limiting resistor should be placed in series with each LED to control the maximum LED current. When not used for controlling the LEDs, these pins may be used as general purpose parallel input/output. RESET: External Reset Input Active low Reset input is used to initialize the 2 CAT9552 internal registers and the I C state machine. The internal registers are held in their default state while Reset input is active. An external pull-up resistor of maximum 25k is required when this pin is not actively driven.
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(c) 2008 SCILLC. All rights reserved Characteristics subject to change without notice
CAT9552 FUNCTIONAL DESCRIPTION
The CAT9552 is a 16-channel I/O bus expander that provides a pair of programmable LED blinkers, controlled through an I2C compatible serial interface. CAT9552 supports the I2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT9552 operates as a Slave device. Both the Master device and Slave device can operate as either transmitter or receiver, but the Master device controls which mode is activated. I C Bus Protocol The features of the I2C bus protocol are defined as follows: (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition (Figure 2). START and STOP Conditions The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of
2
SDA when SCL is HIGH. The CAT9552 monitors the SDA and SCL lines and will not respond until this condition is met. A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. Device Addressing After the bus Master sends a START condition, a slave address byte is required to enable the CAT9552 for a read or write operation. The four most significant bits of the slave address are fixed as binary 1100 (Figure 3). The CAT9552 uses the next three bits as address bits. The address bits A2, A1 and A0 are used to select which device is accessed from maximum eight devices on the same bus. These bits must compare to their hardwired input pins. The 8th bit following the 7bit slave address is the R/W bit that specifies whether a read or write operation is to be performed. When this bit is set to "1", a read operation is initiated, and when set to "0", a write operation is selected. Following the START condition and the slave address byte, the CAT9552 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT9552 then performs a read or a write operation depending on the state of the R/W bit.
SDA
SCL START CONDITION STOP CONDITION
Figure 2. Start/Stop Timing
SLAVE ADDRESS 1 1 0 0 A2 A1 A0 R/W
FIXED
PROGRAMMABLE HARDWARE SELECTABLE
Figure 3. CAT9552 Slave Address
(c) 2008 SCILLC. All rights reserved Characteristics subject to change without notice
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Doc. No. MD-9005 Rev B
CAT9552
Acknowledge After a successful data transfer, each receiving device is required to generate an acknowledge. The acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The SDA line remains stable LOW during the HIGH period of the acknowledge related clock pulse (Figure 4). The CAT9552 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8- bit byte. When the CAT9552 begins a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT9552 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. The master must then issue a stop condition to return the CAT9552 to the standby power mode and place the device in a known state. Registers and Bus Transactions After the successful acknowledgement of the slave address, the bus master will send a command byte to the CAT9552 which will be stored in the Control Register. The format of the Control Register is shown in Figure 5. The Control Register acts as a pointer to determine which register will be written or read. The four least significant bits, B0, B1, B2, B3, are used to select which internal register is accessed, according to the Table 1. If the auto increment flag is set (AI = 1), the four least significant bits of the Control Register are automatically incremented after a read or write operation. This allows the user to access the CAT9552 internal registers sequentially. The content of these bits will rollover to "0000" after the last register is accessed. Table 1. Internal Registers Selection
B3 0 0 0 0 0 0 0 0 1 1 B2 0 0 0 0 1 1 1 1 0 0 B1 0 0 1 1 0 0 1 1 0 0 B0 0 1 0 1 0 1 0 1 0 1 Register Name INPUT0 INPUT1 PSC0 PWM0 PSC1 PWM1 LS0 LS1 LS2 LS3 Type READ READ READ/ WRITE READ/ WRITE READ/ WRITE READ/ WRITE READ/ WRITE READ/ WRITE READ/ WRITE READ/ WRITE Register Function Input Register 0 Input Register 1 Frequency Prescaler 0 PWM Register 0 Frequency Prescaler 1 PWM Register 1 LED 0-3 Selector LED 4-7 Selector LED 8-11 Selector LED 12-15 Selector
SCL FROM MASTER
1
8
9
DATA OUTPUT FROM TRANSMITTER
DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE
Figure 4. Acknowledge Timing
0
0
0
AI
B3
B2
B1
B0
REGISTER ADDRESS RESET STATE: 00h AUTO-INCREMENT FLAG
Figure 5. Control Register
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(c) 2008 SCILLC. All rights reserved Characteristics subject to change without notice
CAT9552
Input Register 0 and Input Register 1 reflect the incoming logic levels of the I/O pins, regardless of whether the pin is defined as an input or an output. These registers are read only ports. Writes to the input registers will be acknowledged but will have no effect. Table 2. Input Register 0 and Input Register 1
INPUT0
LED LED LED LED LED LED LED LED
Table 4. PWM Register 0 and PWM Register 1
PWM0 bit default PWM1 bit default 7 1 6 0 5 0 4 0 3 0 2 0 1 0 0 0 7 1 6 0 5 0 4 0 3 0 2 0 1 0 0 0
7 bit default INPUT1
LED
6 6 X
5 5 X
4 4 X
3 3 X
2 2 X
1 1 X
0 0 X
7 X
Every LED driver output can be programmed to one of four states, LED OFF, LED ON, LED blinks at BLINK0 rate and LED blinks at BLINK1 rate using the LED Selector Registers (Table 5). Table 5. LED Selector Registers
LS0 LED 3 bit 7 0 6 0 5 0 LED 2 4 0 3 0 LED 1 2 0 1 0 LED 0 0 0
LED
LED
LED
LED
LED
LED
LED
15 bit default 7 X
14 6 X
13 5 X
12 4 X
11 3 X
10 2 X
9 1 X
8 0 X
The Frequency Prescaler 0 and Frequency Prescaler 1 registers (PSC0, PSC1) are used to program the period of the pulse width modulated signals BLINK0 and BLINK1 respectively: T_BLINK0 = (PSC0 + 1) / 44; T_BLINK1 = (PSC1 + 1) / 44 Table 3. Frequency Prescaler 0 and Frequency Prescaler 1 Registers
PSC0 bit default PSC1 bit default 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1
default LS1
LED 7 bit default LS2 LED 11 bit default LS3 LED 15 bit default 7 0 6 0 7 0 6 0 7 0 6 0 5 0
LED 6 4 0 3 0
LED 5 2 0 1 0
LED 4 0 0
LED 10 5 0 4 0 3 0
LED 9 2 0 1 0
LED 8 0 0
LED 14 5 0 4 0
LED 13 3 0 2 0
LED 12 1 0 0 0
The PWM Register 0 and PWM Register 1 (PWM0, PWM1) are used to program the duty cycle of BLINK0 and BLINK1 respectively: Duty Cycle_BLINK0 = (256 - PWM0) / 256; Duty Cycle_BLINK1 = (256 - PWM1) / 256 After writing to the PWM0/1 register an 8-bit internal counter starts to count from 0 to 255. The outputs are low (LED on) when the counter value is less than the value programmed into PWM register. The LED is off when the counter value is higher than the value written into PWM register.
The LED output (LED0 to LED15) is set by the 2 bit value from the corresponding LSx Register (x = 0 to 3): 00 = LED Output set LOW (LED On) 01 = LED Output set Hi-Z (LED Off - Default) 10 = LED Output blinks at BLINK0 Rate 11 = LED Output blinks at BLINK1 Rate
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Doc. No. MD-9005 Rev B
CAT9552
Write Operations Data is transmitted to the CAT9552 registers using the write sequence shown in Figure 6. If the AI bit from the command byte is set to "1", the CAT9552 internal registers can be written sequentially. After sending data to one register, the next data byte will be sent to the next register sequentially addressed. Read Operations The CAT9552 registers are read according to the timing diagrams shown in Figure 7 and Figure 8. Data from the register, defined by the command byte, will be sent serially on the SDA line. After the first byte is read, additional data bytes may be read when the auto-increment flag, AI, is set. The additional data byte will reflect the data read from the next register sequentially addressed by the (B3, B2, B1, B0) bits of the command byte. When reading Input Port Registers (Figure 8), data is clocked into the register on the failing edge of the acknowledge clock pulse. The transfer is stopped when the master will not acknowledge the data byte received and issue the STOP condition. LED Pins Used as General Purpose I/O Any LED pins not used to drive LEDs can be used as general purpose input/output, GPIO. When used as input, the user should program the corresponding LED pin to Hi-Z ("01" for the LSx register bits). The pin state can be read via the Input Register according to the sequence shown in Figure 8. For use as a logic output, an external pull-up resistor should be connected to the pin. The value of the pullup resistor is calculated according to the DC operating characteristics. To set the output high, the user has to program the output Hi-Z writing "01" into the corresponding LED Selector (LSx) register bits. The output pin is set low when the output is programmed low through the LSx register bits ("00" in LSx register bits). GPIO can also be used as PWM outputs by setting the LED Selector (LSx) register to "10" or "11" to output either the BLINK0 or BLINK1 waveform.
SCL
1
2
3
4
5
6
7
8
9 Command Byte Data To Register 1 A Acknowledge From Slave DATA 1 A Acknowledge From Slave Data To Register 2 1.0 A
Slave Address SDA S 1 1 0 0 A2 A1 A0 0 R/W A 0 0
0
AI
B3 B2 B1 B0
Start Condition
Acknowledge From Slave
WRITE TO REGISTER DATA OUT FROM PORT tpv
Figure 6. Write to Register Timing Diagram
Acknowledge From Slave Acknowledge From Slave Acknowledge From Slave Acknowledge From Master
Slave Address
S 1 1 0 0 A2 A1 A0
Slave Address
1 1 0 0 A2 A1 A0
Data From Register
DATA
0
A
COMMAND BYTE
A
S
1
A MSB
LSB
A
R/W
R/W At This Moment Master-Transmitter Becomes Master-receiver and Slave-Receiver Becomes Slave-Transmitter
First Byte Auto-increment Register Address If Al = 1 No Acknowledge From Master
LSB NA P
Data From Register
MSB DATA
Note: Transfer can be stopped at any time by a STOP condition.
Last Byte
Figure 7. Read from Register Timing Diagram
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Doc. No. MD-9005 Rev B
(c) 2008 SCILLC. All rights reserved Characteristics subject to change without notice
CAT9552
External Reset Operation The CAT9552 registers and the I2C state machine are initialized to their default state when the RESET input is held low for a minimum of tW. CAT9552's registers will be held in their default state until RESET returns to a logic HIGH state. The external Reset timing is shown in Figure 9. Power-On Reset Operation The CAT9552 incorporates Power-On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. The device is in a reset state for VCC less than the internal POR threshold level (VPOR). When VCC exceeds the VPOR level, the reset state is released and the CAT9552 internal state machine and registers are initialized to their default state. Thereafter VCC must be taken below 0.2V to reset the device.
Data From Port
Slave Address
Data From Port
SDA
S
1
1
0
0
A2
A1 A0 R/W
A Acknowledge From Slave
DATA 1
A Acknowledge From Master
DATA 4
NA No Acknowledge From Master
P Stop Condition
Start Condition
READ FROM PORT
DATA INTO PORT
DATA 1 tph
DATA 2
DATA 3 tps
DATA 4
Figure 8. Read Input Port Register Timing Diagram
START SCL
ACK OR READ CYCLE
SDA
30% tRESET
RESET
50% tREC
50% tW
50%
tRESET LEDx 50% LED OFF
Figure 9. RESET Timing Diagram
(c) 2008 SCILLC. All rights reserved Characteristics subject to change without notice
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Doc. No. MD-9005 Rev B
CAT9552
APPLICATION INFORMATION
Programming Example The following programming sequence is an example how to set: - LED0 to LED3: ON - LED4 to LED7: Blink at 1Hz with a 50% duty cycle (Blink 0) - LED8 to LED11: Blink at 4Hz with a 20% duty cycle (Blink 1) - LED12 to LED15: OFF Command Description START Send Slave address, A0-A2 = low Command Byte: AI="1"; PSC0 Addr Set Blink 0 at 1Hz, T_Blink1 = (PSC0+1)/44 = 1 Write PSC0 = 43 Set PWM0 duty cycle to 50% (256-PWM0) / 256 = 0.5 Write PWM0=128 Set Blink 1 at 4Hz, T_Blink1 = (PSC1+1)/44 = 0.25 Write PSC1 = 10 Set PWM1 duty cycle to 25% (256-PWM1) / 256 = 0.25 Write PWM1=192 Write LS0: LED0 to LED3 = ON Write LS1: LED4 to LED7 at Blink0 Write LS2: LED8 to LED11 at Blink1 Write LS3: LED12 to LED15 = OFF STOP
5V
I2C Data C0h 12h 2Bh
1 2 3 4
5
80h
6
0Ah
7 8 9 10 11 12
C0h 00h AAh FFh 55h
5V
VCC
10k (x 3)
VCC SDA SCL RESET SDA SCL RESET
LED0 LED1 LED2 LED3 LED4 LED5 LED6 LED7 LED8 LED9 LED10 LED11 LED12 LED13 LED14 LED15
Note: LED0 to LED11 are used as LED drivers and LED12 to LED15 are used as regular GPIOs.
GND
CAT9552
I2C/SMBus MASTER
A2 A1 A0 VSS
GPIOs
Figure 10. Typical Application
Doc. No. MD-9005 Rev B
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(c) 2008 SCILLC. All rights reserved Characteristics subject to change without notice
CAT9552
PACKAGE OUTLINE DRAWINGS
SOIC 24-Lead (W) (1)(2)
SYMBOL
MIN
NOM
MAX
A A1 A2 b
E1 E
2.35 0.10 2.05 0.31 0.20 15.20 10.11 7.34 1.27 BSC 0.25 0.40 0 5
2.65 0.30 2.55 0.51 0.33 15.40 10.51 7.60 0.75 1.27 8 15
c D E E1 e h
b PIN#1 IDENTIFICATION
e
L 1
TOP VIEW
D
h
h
1
A
A2
1
A1 SIDE VIEW
L END VIEW
c
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-013.
(c) 2008 SCILLC. All rights reserved Characteristics subject to change without notice
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Doc. No. MD-9005 Rev B
CAT9552
TSSOP 24-Lead 4.4mm (Y) (1)(2)
b
SYMBOL
MIN
NOM
MAX
A A1 A2 b
E1 E
1.20 0.05 0.80 0.19 0.09 7.70 6.25 4.30 7.80 6.40 4.40 0.65 BSC 1.00 REF 0.50 0 0.60 0.70 8 0.15 1.05 0.30 0.20 7.90 6.55 4.50
c D E E1 e L L1 1
e TOP VIEW
D c A2 A 1 L1 L SIDE VIEW END VIEW
A1
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153.
Doc. No. MD-9005 Rev B
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(c) 2008 SCILLC. All rights reserved Characteristics subject to change without notice
CAT9552
TQFN 24-Lead 4 x 4mm (HV6) (1)(2)
D
A DETAIL A
E
E2
PIN#1 ID PIN#1 INDEX AREA TOP VIEW D2
A1 SIDE VIEW
BOTTOM VIEW
b SYMBOL MIN NOM MAX
e
L
A A1 A3 b D D2 E E2 e L
0.70 0.00 0.18 3.90 2.40 3.90 2.40 0.30
0.75 0.02 0.20 REF 0.25 4.00 - 4.00 - 0.50 BSC 0.40
0.80 0.05
DETAIL A
0.30 4.10 2.90 4.10 2.90 0.50
A3 A
FRONT VIEW
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC standard MO-220.
(c) 2008 SCILLC. All rights reserved Characteristics subject to change without notice
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Doc. No. MD-9005 Rev B
CAT9552 EXAMPLE OF ORDERING INFORMATION (1)
Prefix CAT
Company ID
Device # Suffix 9552 HV6
Package W: SOIC, JEDEC Y: TSSOP HV6: TQFN
I
-
G
T2
Tape & Reel T: Tape & Reel 1: 1,000/Reel SOIC only 2: 2,000/Reel
Product Number
Lead Finish Blank: Matte-Tin G: NiPdAu
9552
Temperature Range I = Industrial (-40C to 85C)
ORDERING PART NUMBER
Part Number CAT9552WI CAT9552WI-T1 CAT9552YI CAT9552YI-T2 CAT9552HV6I-G CAT9552HV6I-GT2 Package SOIC SOIC TSSOP TSSOP TQFN TQFN Lead Finish Matte-Tin Matte-Tin Matte-Tin Matte-Tin NiPdAu NiPdAu
For Product Top Mark Codes, click here: http://www.catsemi.com/techsupport/producttopmark.asp
Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard plated finish is Matte-Tin for SOIC and TSSOP packages. The standard plated finish is NiPdAu for TQFN package. (3) The device used in the above example is a CAT9552HV6I-GT2 (TQFN, Industrial Temperature, NiPdAu, Tape & Reel, 2,000/Reel). (4) For additional temperature options, please contact your nearest ON Semiconductor Sales office.
Doc. No. MD-9005 Rev B
16
(c) 2008 SCILLC. All rights reserved Characteristics subject to change without notice
CAT9552
REVISION HISTORY
Date 23-Jun-08 03-Dec-08 Revisio A B Description Initial Issue Update A.C. Characteristics table to include Standard I2C and Fast I2C. Change logo and fine print to ON Semiconductor
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center: Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
(c) 2008 SCILLC. All rights reserved Characteristics subject to change without notice
17
Doc. No. MD-9005, Rev. B

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